RTC clock configuration register
| CK8M_DIV_SEL_VLD | Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock. |
| CK8M_DIV | Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024. |
| ENB_CK8M | Set this bit to disable CK8M and CK8M_D256_OUT. |
| ENB_CK8M_DIV | Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256. |
| DIG_XTAL32K_EN | Set this bit to enable CK_XTAL_32K clock for the digital core. |
| DIG_CLK8M_D256_EN | Set this bit to enable CK8M_D256_OUT clock for the digital core. |
| DIG_CLK8M_EN | Set this bit to enable 8 MHz clock for the digital core. |
| CK8M_DIV_SEL | Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1 |
| XTAL_FORCE_NOGATING | Set this bit to force no gating to crystal during sleep |
| CK8M_FORCE_NOGATING | Set this bit to disable force gating to 8 MHz crystal during sleep. |
| CK8M_DFREQ | CK8M_DFREQ |
| CK8M_FORCE_PD | Set this bit to FPD the 8 MHz clock. |
| CK8M_FORCE_PU | Set this bit to FPU the 8 MHz clock. |
| FAST_CLK_RTC_SEL | Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M. |
| ANA_CLK_RTC_SEL | Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256. |